Semiconductor devices have become progressively more complex, driven at least in part by the demand for smaller sizes and enhanced functionality. While the benefits of smaller sizes and enhanced functionality are apparent, these characteristics of semiconductor devices also can create problems.
In conventional wafer-level packaging, semiconductor devices within a wafer are packaged prior to singulation of the wafer. As such, conventional wafer-level packaging can be restricted to a fan-in configuration, namely electrical contacts and other components of a resulting semiconductor device package are restricted to an area defined by a periphery of a semiconductor device. Any component disposed outside of the periphery of the semiconductor device typically is not supported and typically is removed upon singulation. The restriction of a fan-in configuration presents challenges as device sizes continue to shrink, while device functionality continues to increase.
In conjunction, electronic products typically have to accommodate a high density of semiconductor devices in a limited space. For example, the space available for processors, memory devices, and other active or passive devices can be rather limited in cell phones, personal digital assistants, laptop computers, and other portable consumer products. Packaging of semiconductor devices within semiconductor device packages can take up additional valuable space within electronic products. As such, there is a strong trend towards increasing a density of semiconductor devices for a given footprint area taken up by a semiconductor device package. Unfortunately, conventional wafer-level packaging can be inadequate with respect to addressing this trend.
It is against this background that a need arose to develop the wafer-level semiconductor device packages and related stacked package assemblies and methods described herein.